PIC18F4450T-I/ML【PDF 21/241 页】IC PIC MCU FLASH 8KX16 44QFN

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117

XMEGA A [MANUAL]

8077I–AVR–11/2012

10.6

Register Description

10.6.1 CTRL: Control register

Bit 7: 6 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write this bit to zero

when this register is written.

Bit 5 – HIGHESR: High ESR Mode

Setting this bit will increase the current used to drive the crystal and increase the swing on the TOSC2 pin. This allows

use of crystals with higher load and higher ESR.

Bit 4 – XOSCSEL: Crystal Oscillator Output Selection

This bit selects the prescaled clock output from the 32.768kHz crystal oscillator. After reset, this bit is zero, and the 1Hz

clock output is used as input for the RTC. Setting this bit will select the 1.024kHz clock output as input for the RTC32.

This bit cannot be changed when XOSCEN is set.

Bit 3 – XOSCEN: Crystal Oscillator Enable

Setting this bit will enable the 32.768kHz crystal oscillator. Writing the bit to zero will have no effect, and the oscillator will

remain enabled until a battery backup reset is issued. The Crystal oscillator can also be used as 32.768 kHz system

clock after performing step one to three described in “Configuration” on page 116.

Bit 2 – XOSCFDEN: Crystal Oscillator Failure Detection Enable

Setting this bit will enable the crystal oscillator monitor. The monitor will detect if the crystal is stopped or loses

connection temporarily. At least 64 swings must be lost before the failure detection is triggered. Writing the bit to zero will

have no effect, and the crystal oscillator monitor will remain enabled until a battery backup reset is issued.

Bit 1 – ACCEN: Module Access Enable

Setting this bit will enable access to the battery backup registers. After main reset, this bit must be set in order to access

(read from and write to) the battery backup registers, except for the BBPODF, the BBBODF, and the BBPWR flags,

which are always accessible. Writing this bit to zero will have no effect; only a device reset will clear this bit.

Bit 0 – RESET: Reset

Setting this bit will force a reset of the battery backup system lasting one peripheral clock cycle. Writing the bit to zero will

have no effect. Writing a one to XOSCEN or XOSCFDEN at the same time will block writing to this bit. When this bit is

set, HIGHESR, XOSCSEL, XOSCEN, and XOSCFDEN in CTRL and XOSCRDY in STATUS will be cleared.

This bit is protected by the Configuration Change Protection mechanism. For a detailed description, refer to

“Configuration Change Protection” on page 13.

Bit

+0x00

–

HIGHESR

XOSCSEL

XOSCEN

XOSCFDEN

ACCEN

RESET

Read/Write

R/W

initial Value

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